The present invention relates to a pipeline type A/D converter circuit in which each sub-A/D converter and each sub-D/A converter of low bits are arranged as one block and a plurality of these blocks are cascade-connected, and to a configuration of a resistor ladder circuit for use in such a circuit.
Heretofore, there has been proposed the pipeline type A/D converter circuit technology in which each sub-A/D converter and each sub-D/A converter of low bits are arranged as one block and a plurality of these blocks are cascade-connected. The pipeline type A/D converter circuit is, for example, described in an article 1 of Lewis, S. H., and Gray, P. R., "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," Proceeding of IEEE International Symposium on Circuits and Systems, pp. 954 to 961, 1987.
An example of a circuit configuration of a conventional pipelinetype A/D converter circuit is shown in FIG. 5. In addition, an example of a configuration of a sub-A/D converter circuit which is used in each of blocks is shown in FIG. 6. Also, an example of a conventional configuration of a resistor ladder for reference voltages of the sub-A/D converter circuit is shown in FIG. 7. In this example, there is employed the sub-A/D converter circuit of 2 bits (four divisions). In addition, FIG. 8 is a timing chart showing changes in signals with time in the conventional pipeline type A/D converter circuit.
In FIG. 5, a signal vin (FIG. 8(a)) which has been inputted through an A/D converter circuit input terminal 17 is inputted, after having passed through a sample and hold circuit 1, to both of a sub-A/D converter circuit 2 in the first stage and a multiplying D/A converter circuit (hereinafter, referred to as "an MDAC" for short, when applicable) 14 in the first stage. The signal which has been inputted to the sub-A/D converter circuit 2 is, as shown in FIG. 6, sent through a sub-A/D converter circuit input terminal 33 to one of non-inverting input terminals of comparators 21, 22 and 23. On the other hand, reference voltages 60, 61 and 62 which are produced in a resistor ladder circuit shown in FIG. 7 are respectively inputted through sub-A/D converter circuit reference voltage input terminals 34, 35 and 36 to inverting input terminals of the comparators 21, 22 and 23. In FIG. 7, reference voltages 31 and 32 are divided through resistors 27, 28, 29 and 30 to produce the reference voltages 60, 61 and 62. In addition, the resistor ladder circuit shown in FIG. 7 is commonly used in sub-A/D converter circuits 2, 3, 4 and 53 in the respective stages. In FIG. 6, after each of the comparators 21, 22 and 23 has compared the electric potential at the sub-A/D converter circuit signal input terminal 33 with the electric potentials at the sub-A/D converter circuit reference voltage input terminals 34, 35 and 36 corresponding to the respective comparators, the resulting output signals are inputted to an encoder 24. The output signals from the encoder 24 are, after having been inputted to latches 25 and 26, outputted through sub-A/D converter circuit output terminals 37 and 38. After those output signals have been inputted to a sub-D/A converter circuit 5 shown in FIG. 5 which converts in turn those signals into an analog voltage equivalent to the digital data of 2 bits, an output signal from the sample and hold circuit 1 is subtracted from the analog voltage signal in an addition circuit 11. The output signal from the addition circuit 11 is amplified in an amplification circuit 8 to be inputted through an MDAC output terminal 18 to both of a sub-A/D converter 3 in the second stage and an MDAC 15 in the second stage. The waveform of the signal vout1 at the MDAC output terminal 18 is shown in FIG. 8(b).
The signal which has been inputted through the MDAC output terminal 18 to both of the sub-A/D converter circuit 3 in the second stage and the MDAC 15 in the second stage is processed in the same manner as that in the first stage to be inputted to both of a sub-A/D converter circuit 4 in the third stage and an MDAC 16 in the third stage. The waveform of the signal vout2 at an MDAC output terminal 19 is shown in FIG. 8(c).
The signal which has been inputted through the MDAC output terminal 19 to both of the A/D converter circuit 4 in the third stage and the MDAC 16 in the third stage is processed in the same manner as that in the first stage to be inputted to a sub-A/D converter circuit 53 in the fourth stage. The waveform of the signal vout3 at an MDAC output terminal 20 is shown in FIG. 8(d).
The output signals of the sub-A/D converter circuits 2, 3, 4 and 53 in the respective stages are fetched as the output of the A/D converter circuit through a digital correction circuit 52.